This invention relates to parallel to serial conversion apparatuses that may be used in, for example, high-speed serial communications.
In the field of high-speed serial communications, it is conventional to perform various digital signal processing on low-speed parallel data and, then, convert the processed parallel data to high-speed serial data before transmitting the data to a transmission line. Thereby, the various digital signal processing can be easily performed.
Various types of parallel to serial conversion apparatus are known. For example, Japanese laid-open patent JP 8-65173 (Patent document 1) discloses a type of parallel to serial conversion apparatus constructed with a shift-register. Japanese laid-open patent JP 2002-9629 (Patent document 2) discloses a tree-type parallel to serial conversion apparatus. That is, a plurality of 2:1 parallel to serial conversion circuits, or unit conversion circuits, is arranged in a form of a tree having a plurality of stages.
On the other hand, FIG. 13 of U.S. Pat. No. 7,253,754 (Patent document 3) shows a parallel-serial converter that converts parallel data having a width determined by a dividing ratio setting signal.
Conversion apparatuses disclosed in Patent documents 1 or 3 requires high-speed shift registers that operate at an output frequency. Accordingly, especially when serializing parallel data having wide widths, circuitry that operates at a high-speed increases and the layout design becomes difficult. The conversion apparatus disclosed in Patent document 2 includes circuitry that operates at a high-speed only in the 2:1 multiplexer just before the output. Accordingly, layout design becomes easy and the power consumption decreases. However, a parallel to serial conversion ratio is fixed to 2n, where n is a positive integer.
FIG. 18 of Patent document 3 proposes to utilize the tree-type structure disclosed in Patent document 2 in high-speed operating portions while utilizing the shift-register structure in remaining portions. Thereby, problems caused by the high-speed operation can be solved. However, Patent document 3 only provides a parallel to serial conversion apparatus that converts input parallel data having a fixed width determined by the dividing ratio setting signal. It does not provide a parallel to serial conversion apparatus that can select the width of input parallel data.